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Disambiguation of "Benkrid, Khaled"

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Towards a general framework for FPGA based image processing using hardware skeletons.

, , and . Parallel Computing, 28 (7-8): 1141-1154 (2002)

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Marwan Khaled University of Stuttgart

Khaled Seyam University of Stuttgart

Dipl. Ing. Mohammed Mohamed Khaled Hassan Aly University of Stuttgart

 

Other publications of authors with the same name

Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension., and . IEEE Trans. VLSI Syst., 17 (5): 709-722 (2009)Efficient FPGA hardware development: A multi-language approach., , and . Journal of Systems Architecture, 53 (4): 184-209 (2007)Multiple-clone configuration of relocatable partial bitstreams in Xilinx Virtex FPGAs., , , and . AHS, page 178-183. IEEE, (2013)Rapid Prototyping of an Improved Cholesky Decomposition Based MIMO Detector on FPGAs., , and . AHS, page 369-375. IEEE Computer Society, (2009)An FPGA task allocator with preliminary First-Fit 2D packing algorithms., , , , and . AHS, page 264-270. IEEE, (2011)High performance Intra-task parallelization of Multiple Sequence Alignments on CUDA-compatible GPUs., , and . AHS, page 360-366. IEEE, (2011)Design and Implementation of a Generic 2-D Orthogonal Discrete Wavelet Transform on FPGA., , and . FCCM, page 162-172. IEEE Computer Society, (2003)Efficient architecture and scheduling technique for pairwise sequence alignment., , and . SIGARCH Computer Architecture News, 40 (4): 26-31 (2012)Minimisation and prediction of the error dynamic range in finite wordlength FIR based architectures: application to the 2-D orthogonal DWT., , and . ISSPA (2), page 283-286. IEEE, (2003)0-7803-7946-2.Design and implementation of a novel architecture for symmetric FIR filters with boundary handling on Xilinx Virtex FPGAs., , and . FPT, page 356-359. IEEE, (2002)