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The TH Express high performance interconnect networks.

, , , , , , and . Frontiers of Computer Science, 8 (3): 357-366 (2014)

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DTM: Decoupled Hardware Transactional Memory to Support Unbounded Transaction and Operating System., , , , , and . ICPP, page 228-236. IEEE Computer Society, (2009)Efficient Verification of Parameterized Cache Coherence Protocols., , , and . ICYCS, page 154-159. IEEE Computer Society, (2008)Fine-Grained Location-Free Planarization in Wireless Sensor Networks., , , , and . IEEE Trans. Mob. Comput., 12 (5): 971-983 (2013)A low-latency fine-grained dynamic shared cache management scheme for chip multi-processor., , and . IPCCC, page 1-7. IEEE Computer Society, (2015)The Efficient In-band Management for Interconnect Network in Tianhe-2 System., , , , and . PDP, page 18-26. IEEE Computer Society, (2016)An Area-Efficient DAMQ Buffer with Congestion Control Support., , , , , and . Journal of Circuits, Systems, and Computers, 25 (10): 1650125:1-1650125:25 (2016)A GPDMA-based Distributed Shared I/O Solution for CC-NUMA System., , , , and . ICYCS, page 172-177. IEEE Computer Society, (2008)A Low Overhead Last-Write-Touch Prediction Scheme., , , , and . DASC, page 179-183. IEEE Computer Society, (2014)Inferring Assertion for Complementary Synthesis., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (8): 1288-1292 (2012)Adaptive Bubble Scheme with Minimal Buffers in Torus Networks., , , and . HPCC-ICESS, page 914-919. IEEE Computer Society, (2012)