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Extending Harmless architecture description language for embedded real-time systems validation., , and . SIES, page 223-231. IEEE, (2011)Evaluation of High Performance Multicache Parallel Texture Mapping., , and . International Conference on Supercomputing, page 289-296. ACM, (1998)STM-HRT: A Robust and Wait-Free STM for Hard Real-Time Multicore Embedded Systems., , , , and . ACM Trans. Embedded Comput. Syst., 14 (4): 66:1-66:25 (2015)A Communication Architecture for a Massively Parallel Message-Passing Multicomputer., , , and . J. Parallel Distrib. Comput., 19 (4): 338-348 (1993)Hardware features of the static communication network of a parallel architecture., , , and . Microprocessing and Microprogramming, 38 (1-5): 19-24 (1993)Increasing hardware data prefetching performance using the second-level cache., , and . Journal of Systems Architecture, 48 (4-5): 137-149 (2002)Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces., , and . EUROMICRO, page 409-. IEEE Computer Society, (1997)Hardware runtime verification of embedded software in SoPC., , , , and . SIES, page 171-176. IEEE, (2016)Formal Model-Based Synthesis of Application-Specific Static RTOS., , , and . ACM Trans. Embedded Comput. Syst., 16 (4): 97:1-97:25 (2017)A Parallel Algorithm for 3D Geometry Transformations in OpenGL., , , and . Euro-Par, volume 1685 of Lecture Notes in Computer Science, page 659-662. Springer, (1999)