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Towards Reliable and Secure Post-Quantum Co-Processors based on RISC-V., , , , , and . DATE, page 1148-1153. IEEE, (2019)Model-based framework for networks-on-chip design space exploration., , and . AISTECS@HiPEAC, page 32-35. ACM, (2017)Hierarchical control flow matching for source-level simulation of embedded software., , and . ISSoC, page 1-5. IEEE, (2012)GRIP: grammar-based IP integration and packaging for acceleration-rich SoC designs., , and . DAC, page 46:1-46:6. ACM, (2015)Application-aware cross-layer reliability analysis and optimization., , , , , , , , , and 4 other author(s). it - Information Technology, 57 (3): 159-169 (2015)Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges., , , , , , , , , and 15 other author(s). DAC, page 113:1-113:6. ACM, (2014)Hardware-Accelerated Software Library Drivers Generation for IP-Centric SoC Designs., , , and . ACM Great Lakes Symposium on VLSI, page 287-292. ACM, (2016)Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip., , , , and . INA-OCMC@HiPEAC, page 9-12. IEEE Computer Society, (2015)ACCESS: HW/SW Co-Equivalence Checking for Firmware Optimization., , , , , and . DAC, page 187. ACM, (2019)