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Linear complementary dual code improvement to strengthen encoded circuit against hardware Trojan horses.

, , , , and . HOST, page 82-87. IEEE Computer Society, (2015)

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Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest., , , , , , , , , and 9 other author(s). J. Cryptographic Engineering, 4 (4): 259-274 (2014)Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints., , , , and . DATE, page 640-645. IEEE, (2009)Practical Setup Time Violation Attacks on AES., , and . EDCC, page 91-96. IEEE Computer Society, (2008)Design methodology of an ASIC TRNG based on an open-loop delay chain., , , and . NEWCAS, page 1-4. IEEE, (2013)Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA., , , , and . ICICDT, page 1-4. IEEE, (2015)FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems., , , and . ReConFig, page 47-55. IEEE Computer Society, (2006)Cryptographically Secure Shield for Security IPs Protection., , , , , , and . IEEE Trans. Computers, 66 (2): 354-360 (2017)The Conflicted Usage of RLUTs for Security-Critical Applications on FPGA., , , , , , , and . J. Hardware and Systems Security, 2 (2): 162-178 (2018)Time-Frequency Analysis for Second-Order Attacks., , , , , , , , and . CARDIS, volume 8419 of Lecture Notes in Computer Science, page 108-122. Springer, (2013)"Rank Correction": A New Side-Channel Approach for Secret Key Recovery., , , and . InfoSecHiComNet, volume 7011 of Lecture Notes in Computer Science, page 128-143. Springer, (2011)