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Reliable code generation and execution on unreliable hardware under joint functional and timing reliability considerations.

S. Rehman, A. Toma, F. Kriebel, M. Shafique, J. Chen, and J. Henkel. IEEE Real-Time and Embedded Technology and Applications Symposium, page 273-282. IEEE Computer Society, (2013)

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Florian Lerch University of Stuttgart

Florian Hornung University of Stuttgart

Florian Jaensch University of Stuttgart

Florian Schäfer University of Stuttgart

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ACSEM: accuracy-configurable fast soft error masking analysis in combinatorial circuits.F. Kriebel, S. Rehman, D. Sun, P. Aceituno, M. Shafique, and J. Henkel. DATE, page 824-829. ACM, (2015)ASER: Adaptive Soft Error Resilience for Reliability-Heterogeneous Processors in the Dark Silicon Era.F. Kriebel, S. Rehman, D. Sun, M. Shafique, and J. Henkel. DAC, page 12:1-12:6. ACM, (2014)Hardware and Software Techniques for Heterogeneous Fault-Tolerance.S. Rehman, F. Kriebel, B. Prabakaran, F. Khalid, and M. Shafique. IOLTS, page 115-118. IEEE, (2018)Architectural-Space Exploration of Heterogeneous Reliability and Checkpointing Modes for Out-of-Order Superscalar Processors.B. Prabakaran, M. Dave, F. Kriebel, S. Rehman, and M. Shafique. IEEE Access, (2019)Compiler-driven dynamic reliability management for on-chip systems under variabilities.S. Rehman, F. Kriebel, M. Shafique, and J. Henkel. DATE, page 1-4. European Design and Automation Association, (2014)Revc: Computationally Reliable Video Coding on unreliable hardware platforms: A case study on error-tolerant H.264/AVC CAVLC entropy coding.S. Rehman, M. Shafique, F. Kriebel, and J. Henkel. ICIP, page 397-400. IEEE, (2011)DRVS: Power-efficient reliability management through Dynamic Redundancy and Voltage Scaling under variations.M. Salehi, M. Tavana, S. Rehman, F. Kriebel, M. Shafique, A. Ejlali, and J. Henkel. ISLPED, page 225-230. IEEE, (2015)Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity.K. Chen, J. Chen, F. Kriebel, S. Rehman, M. Shafique, and J. Henkel. IEEE Trans. Computers, 65 (11): 3441-3455 (2016)R2Cache: Reliability-aware reconfigurable last-level cache architecture for multi-cores.F. Kriebel, A. Subramaniyan, S. Rehman, S. Ahandagbe, M. Shafique, and J. Henkel. CODES+ISSS, page 1-10. IEEE, (2015)Reliable code generation and execution on unreliable hardware under joint functional and timing reliability considerations.S. Rehman, A. Toma, F. Kriebel, M. Shafique, J. Chen, and J. Henkel. IEEE Real-Time and Embedded Technology and Applications Symposium, page 273-282. IEEE Computer Society, (2013)