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Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling., , , and . DATE, page 911-916. IEEE, (2009)Layout-Driven RTL Binding Techniques for High-Level Synthesis., and . ISSS, page 33-38. ACM / IEEE Computer Society, (1996)Incorporating the Controller Effects During Register Transfer Level Synthesis., and . EDAC-ETC-EUROASIC, page 308-313. IEEE Computer Society, (1994)Kernel Scheduling in Reconfigurable Computing., , , , , and . DATE, page 90-96. IEEE Computer Society / ACM, (1999)On combining iteration space tiling with data space tiling for scratch-pad memory systems., and . ASP-DAC, page 973-976. ACM Press, (2005)Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations., , , , , and . CODES+ISSS, page 257-266. ACM, (2011)A comprehensive estimation technique for high-level synthesis., , , and . ISSS, page 122-127. ACM, (1995)Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization., , , , and . ISSS, page 107-114. ACM / IEEE Computer Society, (2000)Module assignment and interconnect sharing in register-transfer synthesis of pipelined data paths., and . ICCAD, page 16-19. IEEE Computer Society, (1989)Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs., , , , , and . Asia-Pacific Computer Systems Architecture Conference, volume 4186 of Lecture Notes in Computer Science, page 295-308. Springer, (2006)