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Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains., and . IEEE Trans. VLSI Syst., 22 (3): 641-654 (2014)Private reliability environments for efficient fault-tolerance in CGRAs., , , , , and . Design Autom. for Emb. Sys., 18 (3-4): 295-327 (2014)System Level Virtual Prototyping of DSP SOCs Using Grammar Based Approach., , , , , and . Design Autom. for Emb. Sys., 5 (3-4): 295-311 (2000)Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes., , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 37 (8-A): 811-822 (2013)Grammar-Based Hardware Synthesis of Data Communication Protocols., , and . ISSS, page 14-19. ACM / IEEE Computer Society, (1996)Morphable DPU: Smart and efficient data path for signal processing applications., and . SiPS, page 167-172. IEEE, (2009)A GALS Network-on-Chip based on rationally-related frequencies., and . ICCD, page 12-18. IEEE Computer Society, (2011)Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation., , , , , and . PECCS, page 450-458. SciTePress, (2012)A neural net based self organising scheduling algorithm., and . EURO-DAC, page 136-140. IEEE Computer Society, (1990)Hardware/software partitioning and minimizing memory interface traffic., , , , and . EURO-DAC, page 226-231. IEEE Computer Society, (1994)