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The challenges of using an embedded MPI for hardware-based processing nodes.

, , and . FPT, page 120-127. IEEE Computer Society, (2009)

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Exploring pipe implementations using an OpenCL framework for FPGAs., and . FPT, page 112-119. IEEE, (2015)Accelerating Apache Spark with FPGAs., and . Concurrency and Computation: Practice and Experience, (2019)Virtualized Reconfigurable Hardware Resources in the SAVI Testbed., , , , and . TRIDENTCOM, volume 137 of Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, page 54-64. Springer, (2014)RACER: a reconfigurable constraint-length 14 Viterbi decoder., , and . FCCM, page 60-69. IEEE, (1996)A high-performance architecture for training Viola-Jones object detectors., and . FPT, page 174-181. IEEE, (2012)An efficient FPGA implementation of QR decomposition using a novel systolic array architecture based on enhanced vectoring CORDIC., , and . FPT, page 123-130. IEEE, (2014)Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python method., , , , and . FPT, page 190-197. IEEE, (2012)Caffeinated FPGAs: FPGA Framework For Convolutional Neural Networks., , , , , and . CoRR, (2016)A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data Center., , , and . FPGA, page 262-271. ACM, (2019)The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System., , , , and . FPGA, page 53-61. ACM, (1997)