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Disambiguation of "Das, Sabyasachi"

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A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions.

, and . VLSI Design, page 635-640. IEEE Computer Society, (2008)

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Ph. D. Subhasish Das University of Stuttgart

Ph. D. Durga Dasari University of Stuttgart

Pavan Kumar Dasari University of Stuttgart

Dr. Alexandra Fidalgo das Neves University of Stuttgart

 

Other publications of authors with the same name

A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic., and . IEEE Trans. VLSI Syst., 16 (3): 326-331 (2008)A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters., and . VLSI Design, page 572-579. IEEE Computer Society, (2008)Resource sharing among mutually exclusive sum-of-product blocks for area reduction., and . ACM Trans. Design Autom. Electr. Syst., 13 (3): 51:1-51:7 (2008)Trends in Codon and Amino Acid Usage in Human Pathogen Tropheryma Whipplei, the only Known Actinobacteria with Reduced Genome., , and . APBC, page 139-148. Imperial College Press, London, (2006)A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions., and . VLSI Design, page 635-640. IEEE Computer Society, (2008)Consequences of Mutation, Selection, and Physico-Chemical Properties of Encoded Proteins on Synonymous Codon Usage in Adenoviruses., , and . APBC, page 149-158. Imperial College Press, London, (2006)An efficient and regular routing methodology for datapath designsusing net regularity extraction., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 21 (1): 93-101 (2002)A regularity-driven fast gridless detailed router for high frequency datapath designs., and . ISPD, page 130-135. ACM, (2001)Pseudo-BIST: A Novel Technique for SAR-ADC Testing., , , , , and . VDAT, volume 711 of Communications in Computer and Information Science, page 168-178. Springer, (2017)A Timing-Driven Approach to Synthesize Fast Barrel Shifters., and . IEEE Trans. on Circuits and Systems, 55-II (1): 31-35 (2008)