PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Bertrand, Yves"

Author of the publication

copydeleteadd this publication to your clipboard
Hardware Resource Minimization for Histogram-Based ADC BIST.

, , , and . VTS, page 247-254. IEEE Computer Society, (2000)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dr. -Ing. Reinhold Bertrand University of Stuttgart

Yves Klett

 

Other publications of authors with the same name

A New Methodology For ADC Test Flow Optimization., , , , and . ITC, page 201-209. IEEE Computer Society, (2003)Algebraic Specification of a 3D-Modeler Based on Hypermaps., and . CVGIP: Graphical Model and Image Processing, 56 (1): 29-60 (1994)Delay Testing Viability of Gate Oxide Short Defects., , , and . J. Comput. Sci. Technol., 20 (2): 195-200 (2005)Remote Labs for Industrial IC Testing., , , , and . TLT, 2 (4): 304-311 (2009)A-to-D converters static error detection from dynamic parameter measurement., , , , and . Microelectronics Journal, 34 (10): 945-953 (2003)Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST., , , and . J. Electronic Testing, 17 (3-4): 255-266 (2001)Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits., , and . DATE, page 815-821. IEEE Computer Society, (1998)On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems., , , and . DATE, page 1120. IEEE Computer Society, (2002)A Low-Cost Adaptive Ramp Generator for Analog BIST Applications., , , , and . VTS, page 266-271. IEEE Computer Society, (2001)Serial transistor network modeling for bridging fault simulation., , and . Asian Test Symposium, page 100-106. IEEE Computer Society, (1995)