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From Instruction Traces to Specialized Reconfigurable Arrays.

, , , and . ReConFig, page 386-391. IEEE Computer Society, (2011)

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Architecture for Transparent Binary Acceleration of Loops with Memory Accesses., , and . ARC, volume 7806 of Lecture Notes in Computer Science, page 122-133. Springer, (2013)Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces., , and . IEEE Trans. VLSI Syst., 25 (1): 21-34 (2017)Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units., , , and . Int. J. Reconfig. Comp., (2013)Transparent acceleration of program execution using reconfigurable hardware., , , and . DATE, page 1066-1071. ACM, (2015)From Instruction Traces to Specialized Reconfigurable Arrays., , , and . ReConFig, page 386-391. IEEE Computer Society, (2011)Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems., , , and . IEEE Trans. Industrial Informatics, 9 (3): 1625-1634 (2013)Dynamic Partial Reconfiguration of Customized Single-Row Accelerators., , and . IEEE Trans. VLSI Syst., 27 (1): 116-125 (2019)Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support., , and . ISPA, page 158-165. IEEE Computer Society, (2014)A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses., , and . TRETS, 7 (4): 29:1-29:20 (2015)