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Design optimization and space minimization considering timing and code size via retiming and unfolding.

, , , , , and . Microprocessors and Microsystems, 30 (4): 173-183 (2006)

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Optimizing parallelism for nested loops with iterational and instructional retiming., , , , and . J. Embedded Computing, 3 (1): 29-37 (2009)General Loop Fusion Technique with Improved Timing Performance and Minimal Code Size., , , and . I. J. Comput. Appl., 19 (1): 61-76 (2012)Multi-level Loop Fusion with Minimal Code Size., , , , and . ISCA PDCS, page 348-. ISCA, (2005)Loop Fusion via Retiming for DSP Applications., , , , and . ISCA PDCS, page 403-408. ISCA, (2004)Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability., , , , , and . ASAP, page 178-181. IEEE Computer Society, (2006)Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units., , , , , and . IPDPS, IEEE Computer Society, (2004)Loop Distribution and Fusion with Timing and Code Size Optimization., , , , and . Signal Processing Systems, 62 (3): 325-340 (2011)Fast Document Cosine Similarity Self-Join on GPUs., , , , and . ICTAI, page 205-212. IEEE, (2018)Algorithms and analysis of scheduling for loops with minimum switching., , , , , and . IJCSE, 2 (1/2): 88-97 (2006)Design optimization and space minimization considering timing and code size via retiming and unfolding., , , , , and . Microprocessors and Microsystems, 30 (4): 173-183 (2006)