Abstract
Excessive IR-drop during scan shift can cause localized
IR-drop around clock buffers and introduce dynamic
clock skew. Excessive clock skew at neighboring scan flip-flops
results in hold or setup timing violations corrupting test stimuli
or test responses during shifting. We introduce a new method
to assess the risk of such test data corruption at each scan
cycle and flip-flop. The most likely cases of test data corruption
are mitigated in a non-intrusive way by selective test data
manipulation and masking of affected responses. Evaluation
results show the computational feasibility of our method for large
benchmark circuits, and demonstrate that a few targeted pattern
changes provide large potential gains in shift safety and test time
with negligible cost in fault coverage.
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