%0 Conference Paper %1 conf/iscas/ChenHC04 %A Chen, Tung-Chien %A Huang, Yu-Wen %A Chen, Liang-Gee %B ISCAS (2) %D 2004 %I IEEE %K dblp %P 273-276 %T Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2004-2.html#ChenHC04 %@ 0-7803-8251-X

@inproceedings{conf/iscas/ChenHC04, added-at = {2016-05-20T00:00:00.000+0200}, author = {Chen, Tung-Chien and Huang, Yu-Wen and Chen, Liang-Gee}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2a44f8af218a607e98b7c9d65f4bf7eb3/dblp}, booktitle = {ISCAS (2)}, crossref = {conf/iscas/2004}, ee = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9255}, interhash = {af6d2e51cf6932c7de6a9fd56781ebe2}, intrahash = {a44f8af218a607e98b7c9d65f4bf7eb3}, isbn = {0-7803-8251-X}, keywords = {dblp}, pages = {273-276}, publisher = {IEEE}, timestamp = {2016-05-21T09:44:18.000+0200}, title = {Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2004-2.html#ChenHC04}, year = 2004 }