%0 Journal Article %1 elogail2018enhancement %A Elogail, Yasmine %A Fischer, Inga A %A Wendav, Torsten %A Schulze, Jörg %D 2018 %J Semiconductor Science and Technology %K iht j.schulze.iht journal %N 11 %P 114001 %R 10.1088/1361-6641/aae001 %T Enhancement of Ge-based p-channel vertical FET performance by channel engineering using planar doping and a Ge/Si x Ge 1– x – y Sn y heterostructure model for low power FET applications %U http://stacks.iop.org/0268-1242/33/i=11/a=114001 %V 33 %X High mobility materials are being studied to replace Si with the aim of enhancing the performance of nanoelectronic devices. Ge and III–V channels have recently received a lot of attention, where the combination of III–V channels in n-MOSFETs and Ge channels in p-MOSFETs integrated on Si substrates is regarded as a promising CMOS design. Ge integrated on Si is a very promising choice due to its superior transport properties and compatibility to CMOS technology. The main challenges faced by Ge-based FETs are the channel/gate interface quality, crystal defects due to integration on Si and the smaller bandgap compared to Si, which leads to elevated band-to-band-tunnelling leakage currents, setting limitations on the achievable off state current ( I OFF ). In this work, we present results on the fabrication and characterization of vertical Ge-based p-channel planar doped barrier FET together with a simulation model based on extracted material data from our experimental work and literature. Based on the model, a design of a modified device using both planar doping and a heterostructure in the channel is presented. The channel engineered design uses a Ge/Si x Ge 1– x – y Sn y heterostructure, which is lattice matched to Ge, within the channel at different positions. The results show improved performance; the larger bandgap of the ternary alloy Si x Ge 1– x – y Sn y compared to Ge leads to a suppression of the I OFF as well as a reduced subthreshold swing, making the heterostructure device promising for energy efficient FET applications.

@article{elogail2018enhancement, abstract = {High mobility materials are being studied to replace Si with the aim of enhancing the performance of nanoelectronic devices. Ge and III–V channels have recently received a lot of attention, where the combination of III–V channels in n-MOSFETs and Ge channels in p-MOSFETs integrated on Si substrates is regarded as a promising CMOS design. Ge integrated on Si is a very promising choice due to its superior transport properties and compatibility to CMOS technology. The main challenges faced by Ge-based FETs are the channel/gate interface quality, crystal defects due to integration on Si and the smaller bandgap compared to Si, which leads to elevated band-to-band-tunnelling leakage currents, setting limitations on the achievable off state current ( I OFF ). In this work, we present results on the fabrication and characterization of vertical Ge-based p-channel planar doped barrier FET together with a simulation model based on extracted material data from our experimental work and literature. Based on the model, a design of a modified device using both planar doping and a heterostructure in the channel is presented. The channel engineered design uses a Ge/Si x Ge 1– x – y Sn y heterostructure, which is lattice matched to Ge, within the channel at different positions. The results show improved performance; the larger bandgap of the ternary alloy Si x Ge 1– x – y Sn y compared to Ge leads to a suppression of the I OFF as well as a reduced subthreshold swing, making the heterostructure device promising for energy efficient FET applications.}, added-at = {2018-11-19T18:12:48.000+0100}, author = {Elogail, Yasmine and Fischer, Inga A and Wendav, Torsten and Schulze, Jörg}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2fcd570ee99b61b0e1c42e0c800aca267/ihtpublikation}, doi = {10.1088/1361-6641/aae001}, interhash = {8c2812958ecfd8fbf6e2b1265ae29536}, intrahash = {fcd570ee99b61b0e1c42e0c800aca267}, journal = {Semiconductor Science and Technology}, keywords = {iht j.schulze.iht journal}, number = 11, pages = 114001, timestamp = {2018-11-19T17:12:48.000+0100}, title = {Enhancement of Ge-based p-channel vertical FET performance by channel engineering using planar doping and a Ge/Si x Ge 1– x – y Sn y heterostructure model for low power FET applications}, url = {http://stacks.iop.org/0268-1242/33/i=11/a=114001}, volume = 33, year = 2018 }