High mobility materials are being studied to replace Si with the aim of enhancing the performance of nanoelectronic devices. Ge and III–V channels have recently received a lot of attention, where the combination of III–V channels in n-MOSFETs and Ge channels in p-MOSFETs integrated on Si substrates is regarded as a promising CMOS design. Ge integrated on Si is a very promising choice due to its superior transport properties and compatibility to CMOS technology. The main challenges faced by Ge-based FETs are the channel/gate interface quality, crystal defects due to integration on Si and the smaller bandgap compared to Si, which leads to elevated band-to-band-tunnelling leakage currents, setting limitations on the achievable off state current ( I OFF ). In this work, we present results on the fabrication and characterization of vertical Ge-based p-channel planar doped barrier FET together with a simulation model based on extracted material data from our experimental work and literature. Based on the model, a design of a modified device using both planar doping and a heterostructure in the channel is presented. The channel engineered design uses a Ge/Si x Ge 1– x – y Sn y heterostructure, which is lattice matched to Ge, within the channel at different positions. The results show improved performance; the larger bandgap of the ternary alloy Si x Ge 1– x – y Sn y compared to Ge leads to a suppression of the I OFF as well as a reduced subthreshold swing, making the heterostructure device promising for energy efficient FET applications.