This paper describes the implementation and measurement results of a 1.92 GS/s continuous-time (CT) low-pass ΔΣmodulator for a high frequency (>10 GHz) multifunctional receiver. The proposed single-loop 3rd-order modulator operates at 1.92 GHz, taking advantage of the high transit frequency (fT) of a low-cost 0.25 μm SiGe BiCMOS process. In order to achieve high linearity, single-bit quantization is employed, which is inherently linear and no digital DAC linearity enhancement technique is required. The experimental prototype chip achieves a dynamic range of 70 dB and a spurious-free dynamic range (SFDR) of 78.1 dB for a signal bandwidth of 15 MHz. It dissipates 220 mW and occupies 0.4 mm2 silicon area.
%0 Conference Paper
%1 6934087
%A Chu, C.
%A Kauffman, J. G.
%A Anders, J.
%A Becker, J.
%A Ortmanns, M.
%A Epp, M.
%A Chartier, S.
%B 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)
%D 2014
%K delta modulators sigma
%P 480-483
%R 10.1109/NEWCAS.2014.6934087
%T A 1.92-GS/s CT ΔΣ modulator with 70-db DR and 78-db SFDR in 15-MHz bandwidth
%U https://ieeexplore.ieee.org/document/6934087/
%X This paper describes the implementation and measurement results of a 1.92 GS/s continuous-time (CT) low-pass ΔΣmodulator for a high frequency (>10 GHz) multifunctional receiver. The proposed single-loop 3rd-order modulator operates at 1.92 GHz, taking advantage of the high transit frequency (fT) of a low-cost 0.25 μm SiGe BiCMOS process. In order to achieve high linearity, single-bit quantization is employed, which is inherently linear and no digital DAC linearity enhancement technique is required. The experimental prototype chip achieves a dynamic range of 70 dB and a spurious-free dynamic range (SFDR) of 78.1 dB for a signal bandwidth of 15 MHz. It dissipates 220 mW and occupies 0.4 mm2 silicon area.
@inproceedings{6934087,
abstract = {This paper describes the implementation and measurement results of a 1.92 GS/s continuous-time (CT) low-pass ΔΣmodulator for a high frequency (>10 GHz) multifunctional receiver. The proposed single-loop 3rd-order modulator operates at 1.92 GHz, taking advantage of the high transit frequency (fT) of a low-cost 0.25 μm SiGe BiCMOS process. In order to achieve high linearity, single-bit quantization is employed, which is inherently linear and no digital DAC linearity enhancement technique is required. The experimental prototype chip achieves a dynamic range of 70 dB and a spurious-free dynamic range (SFDR) of 78.1 dB for a signal bandwidth of 15 MHz. It dissipates 220 mW and occupies 0.4 mm2 silicon area.},
added-at = {2020-10-11T10:15:09.000+0200},
author = {{Chu}, C. and {Kauffman}, J. G. and {Anders}, J. and {Becker}, J. and {Ortmanns}, M. and {Epp}, M. and {Chartier}, S.},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2b0860f006aa1ae2b408ca57c64e4efff/jens.anders},
booktitle = {2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)},
doi = {10.1109/NEWCAS.2014.6934087},
interhash = {6dd2a52a413202b06096adb5bd4e4957},
intrahash = {b0860f006aa1ae2b408ca57c64e4efff},
keywords = {delta modulators sigma},
month = {June},
pages = {480-483},
timestamp = {2020-10-12T13:46:34.000+0200},
title = {A 1.92-GS/s CT ΔΣ modulator with 70-db DR and 78-db SFDR in 15-MHz bandwidth},
url = {https://ieeexplore.ieee.org/document/6934087/},
year = 2014
}