We present a chip-integrated receiver for electron paramagnetic resonance (EPR), designed for operation in the S-band (2-4 GHz). This EPR-on-a-chip receiver consists of a low-noise amplifier, followed by quadrature downconversion mixers and intermediate-frequency variable gain amplifiers. It also incorporates a frequency generation block. The chip is realized in a $0.13-m$ SiGe BiCMOS technology and occupies an area of $1100 900\ m^2$. The receiver's measured input-referred voltage noise density within the band of interest is $720 pV/\textHz$. Proof-of-concept EPR measurements validate the proposed approach.
%0 Conference Paper
%1 9665504
%A Krüger, Daniel
%A Dreyer, Frederik
%A Kern, Michal
%A Anders, Jens
%B 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)
%D 2021
%I IEEE
%K from:michalkern myown
%P 1-5
%R 10.1109/ICECS53924.2021.9665504
%T An S-band EPR-on-a-chip Receiver in 0.13 μm BiCMOS
%X We present a chip-integrated receiver for electron paramagnetic resonance (EPR), designed for operation in the S-band (2-4 GHz). This EPR-on-a-chip receiver consists of a low-noise amplifier, followed by quadrature downconversion mixers and intermediate-frequency variable gain amplifiers. It also incorporates a frequency generation block. The chip is realized in a $0.13-m$ SiGe BiCMOS technology and occupies an area of $1100 900\ m^2$. The receiver's measured input-referred voltage noise density within the band of interest is $720 pV/\textHz$. Proof-of-concept EPR measurements validate the proposed approach.
@inproceedings{9665504,
abstract = {We present a chip-integrated receiver for electron paramagnetic resonance (EPR), designed for operation in the S-band (2-4 GHz). This EPR-on-a-chip receiver consists of a low-noise amplifier, followed by quadrature downconversion mixers and intermediate-frequency variable gain amplifiers. It also incorporates a frequency generation block. The chip is realized in a $0.13-\mu \mathrm{m}$ SiGe BiCMOS technology and occupies an area of $1100 \times 900\ \mu \mathrm{m}^{2}$. The receiver's measured input-referred voltage noise density within the band of interest is $720 \text{pV}/\sqrt{\text{Hz}}$. Proof-of-concept EPR measurements validate the proposed approach.},
added-at = {2023-07-28T14:11:00.000+0200},
author = {Krüger, Daniel and Dreyer, Frederik and Kern, Michal and Anders, Jens},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2af67a9ddc10ec792e38926fea2260396/iis},
booktitle = {2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)},
doi = {10.1109/ICECS53924.2021.9665504},
interhash = {c47cd8b234eeda3692bbca9ac5b6ef99},
intrahash = {af67a9ddc10ec792e38926fea2260396},
keywords = {from:michalkern myown},
month = nov,
pages = {1-5},
publisher = {IEEE},
timestamp = {2023-07-28T14:11:00.000+0200},
title = {An S-band EPR-on-a-chip Receiver in 0.13 μm BiCMOS},
year = 2021
}
