The p-Ge layers are epitaxially grown by MBE over the n-Ge and strain-free Ge buffer layers on the Si substrate. The drain-source & channel mesa is patterned in the p-Ge layer to create the raised active channel. Post-plasma oxidation was carried out to improve the interface properties of Ge channel. The proposed process doesn't involve source-drain implants, ease channel patterning using MAPDST, a -ve tone resist with high etch resistance and selectivity w.r.t. Ge. The process flow scheme will utilize the “beyond Si” channel materials over Si substrates, concurrently exploiting the standard well, established state-of-art Si CMOS fabrication technology.
Description
Process Optimizations for Ge-On-Si Depletion Mode Transistors Using Mesa Architecture | IEEE Conference Publication | IEEE Xplore
%0 Conference Paper
%1 10027013
%A Choudhary, Sumit
%A Schwarz, Daniel
%A Funk, Hannes S.
%A Sharma, Kumar Palit
%A Sharma, Satinder K.
%A Schulze, Jöorg
%B 2022 International Symposium on Semiconductor Manufacturing (ISSM)
%D 2022
%K iht professional_meetings
%P 1-4
%R 10.1109/ISSM55802.2022.10027013
%T Process Optimizations for Ge-On-Si Depletion Mode Transistors Using Mesa Architecture
%X The p-Ge layers are epitaxially grown by MBE over the n-Ge and strain-free Ge buffer layers on the Si substrate. The drain-source & channel mesa is patterned in the p-Ge layer to create the raised active channel. Post-plasma oxidation was carried out to improve the interface properties of Ge channel. The proposed process doesn't involve source-drain implants, ease channel patterning using MAPDST, a -ve tone resist with high etch resistance and selectivity w.r.t. Ge. The process flow scheme will utilize the “beyond Si” channel materials over Si substrates, concurrently exploiting the standard well, established state-of-art Si CMOS fabrication technology.
@inproceedings{10027013,
abstract = {The p-Ge layers are epitaxially grown by MBE over the n-Ge and strain-free Ge buffer layers on the Si substrate. The drain-source & channel mesa is patterned in the p-Ge layer to create the raised active channel. Post-plasma oxidation was carried out to improve the interface properties of Ge channel. The proposed process doesn't involve source-drain implants, ease channel patterning using MAPDST, a -ve tone resist with high etch resistance and selectivity w.r.t. Ge. The process flow scheme will utilize the “beyond Si” channel materials over Si substrates, concurrently exploiting the standard well, established state-of-art Si CMOS fabrication technology.},
added-at = {2023-11-07T08:14:48.000+0100},
author = {Choudhary, Sumit and Schwarz, Daniel and Funk, Hannes S. and Sharma, Kumar Palit and Sharma, Satinder K. and Schulze, Jöorg},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/22955e7b3b8168776462bdc6d0ab487a8/ihtpublikation},
booktitle = {2022 International Symposium on Semiconductor Manufacturing (ISSM)},
description = {Process Optimizations for Ge-On-Si Depletion Mode Transistors Using Mesa Architecture | IEEE Conference Publication | IEEE Xplore},
doi = {10.1109/ISSM55802.2022.10027013},
interhash = {3c1f48cc68d9f6d070420927763e6e8b},
intrahash = {2955e7b3b8168776462bdc6d0ab487a8},
issn = {1523-553X},
keywords = {iht professional_meetings},
month = dec,
pages = {1-4},
timestamp = {2023-11-07T08:14:48.000+0100},
title = {Process Optimizations for Ge-On-Si Depletion Mode Transistors Using Mesa Architecture},
year = 2022
}
