%0 Journal Article %1 journals/tvlsi/NairBT19 %A Nair, Sarath Mohanachandran %A Bishnoi, Rajendra %A Tahoori, Mehdi Baradaran %D 2019 %J IEEE Trans. VLSI Syst. %K dblp %N 7 %P 1697-1710 %T A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi27.html#NairBT19 %V 27

@article{journals/tvlsi/NairBT19, added-at = {2019-07-05T00:00:00.000+0200}, author = {Nair, Sarath Mohanachandran and Bishnoi, Rajendra and Tahoori, Mehdi Baradaran}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/292f4c40ec1a5b9c15ad4730a36921602/dblp}, ee = {https://doi.org/10.1109/TVLSI.2019.2904197}, interhash = {f6caf16d00ae339b56046e441e1627c1}, intrahash = {92f4c40ec1a5b9c15ad4730a36921602}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 7, pages = {1697-1710}, timestamp = {2019-09-27T06:53:31.000+0200}, title = {A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi27.html#NairBT19}, volume = 27, year = 2019 }