%0 Journal Article %1 journals/jolpe/MajzoubTH19 %A Majzoub, Sohaib %A Taouil, Mottaqiallah %A Hamdioui, Said %D 2019 %J J. Low Power Electronics %K dblp %N 1 %P 1-10 %T System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation. %U http://dblp.uni-trier.de/db/journals/jolpe/jolpe15.html#MajzoubTH19 %V 15

@article{journals/jolpe/MajzoubTH19, added-at = {2019-05-20T00:00:00.000+0200}, author = {Majzoub, Sohaib and Taouil, Mottaqiallah and Hamdioui, Said}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2f4534fbc8a51d3c9d0a417879f6bab65/dblp}, ee = {https://doi.org/10.1166/jolpe.2019.1590}, interhash = {f17e2ee5544a397094242057ef5d2365}, intrahash = {f4534fbc8a51d3c9d0a417879f6bab65}, journal = {J. Low Power Electronics}, keywords = {dblp}, number = 1, pages = {1-10}, timestamp = {2019-09-27T10:38:34.000+0200}, title = {System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation.}, url = {http://dblp.uni-trier.de/db/journals/jolpe/jolpe15.html#MajzoubTH19}, volume = 15, year = 2019 }