%0 Conference Paper %1 conf/socc/YehCHWLL07 %A Yeh, Chi-Yi %A Chen, Hung-Ming %A Huang, Li-Da %A Wei, Wei-Ting %A Lu, Chao-Hung %A Liu, Chien-Nan Jimmy %B SoCC %D 2007 %I IEEE %K dblp %P 233-236 %T Using power gating techniques in area-array SoC floorplan design. %U http://dblp.uni-trier.de/db/conf/socc/socc2007.html#YehCHWLL07 %@ 978-1-4244-1592-2

@inproceedings{conf/socc/YehCHWLL07, added-at = {2012-05-22T00:00:00.000+0200}, author = {Yeh, Chi-Yi and Chen, Hung-Ming and Huang, Li-Da and Wei, Wei-Ting and Lu, Chao-Hung and Liu, Chien-Nan Jimmy}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2f69ac50b1c2918710356b278a2b37ebf/dblp}, booktitle = {SoCC}, crossref = {conf/socc/2007}, ee = {http://dx.doi.org/10.1109/SOCC.2007.4545465}, interhash = {efa795d457e517d2f8d639aa666097bc}, intrahash = {f69ac50b1c2918710356b278a2b37ebf}, isbn = {978-1-4244-1592-2}, keywords = {dblp}, pages = {233-236}, publisher = {IEEE}, timestamp = {2016-02-02T11:49:45.000+0100}, title = {Using power gating techniques in area-array SoC floorplan design.}, url = {http://dblp.uni-trier.de/db/conf/socc/socc2007.html#YehCHWLL07}, year = 2007 }