%0 Journal Article %1 journals/tcad/KohlerSR10 %A Kohler, Adán %A Schley, Gert %A Radetzki, Martin %D 2010 %J IEEE Trans. on CAD of Integrated Circuits and Systems %K dblp %N 6 %P 883-896 %T Fault Tolerant Network on Chip Switching With Graceful Performance Degradation. %U http://dblp.uni-trier.de/db/journals/tcad/tcad29.html#KohlerSR10 %V 29

@article{journals/tcad/KohlerSR10, added-at = {2011-01-12T00:00:00.000+0100}, author = {Kohler, Adán and Schley, Gert and Radetzki, Martin}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2eb2c0cb33eac1cb224d856b2cfa29d0e/dblp}, ee = {http://dx.doi.org/10.1109/TCAD.2010.2048399}, interhash = {e462e5037f9304fd09cc8e565c6fbf3c}, intrahash = {eb2c0cb33eac1cb224d856b2cfa29d0e}, journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, keywords = {dblp}, number = 6, pages = {883-896}, timestamp = {2016-02-02T10:08:28.000+0100}, title = {Fault Tolerant Network on Chip Switching With Graceful Performance Degradation.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad29.html#KohlerSR10}, volume = 29, year = 2010 }