%0 Journal Article %1 journals/tcad/ZhouL04 %A Zhou, Hai %A Lin, Chuan %D 2004 %J IEEE Trans. on CAD of Integrated Circuits and Systems %K dblp %N 9 %P 1338-1345 %T Retiming for wire pipelining in system-on-chip. %U http://dblp.uni-trier.de/db/journals/tcad/tcad23.html#ZhouL04 %V 23

@article{journals/tcad/ZhouL04, added-at = {2016-03-18T00:00:00.000+0100}, author = {Zhou, Hai and Lin, Chuan}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2c3f798cb0ac5a0699e8ad0f7215a7a3e/dblp}, ee = {http://dx.doi.org/10.1109/TCAD.2004.833615}, interhash = {dd971ddec2830043d07d14c3c128e453}, intrahash = {c3f798cb0ac5a0699e8ad0f7215a7a3e}, journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, keywords = {dblp}, number = 9, pages = {1338-1345}, timestamp = {2016-03-19T10:32:45.000+0100}, title = {Retiming for wire pipelining in system-on-chip.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad23.html#ZhouL04}, volume = 23, year = 2004 }