%0 Conference Paper %1 conf/vts/DiJ93 %A Di, Chennian %A Jess, Jochen A. G. %B VTS %D 1993 %I IEEE Computer Society %K dblp %P 116-119 %T On CMOS bridge fault modeling and test pattern evaluation. %U http://dblp.uni-trier.de/db/conf/vts/vts1993.html#DiJ93 %@ 0-8186-3830-3

@inproceedings{conf/vts/DiJ93, added-at = {2019-02-15T00:00:00.000+0100}, author = {Di, Chennian and Jess, Jochen A. G.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2c21b6832c6e387088d47ec2dfa8a4d2f/dblp}, booktitle = {VTS}, crossref = {conf/vts/1993}, ee = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1993.313297}, interhash = {b034f743b66bcd21be633d357f35d667}, intrahash = {c21b6832c6e387088d47ec2dfa8a4d2f}, isbn = {0-8186-3830-3}, keywords = {dblp}, pages = {116-119}, publisher = {IEEE Computer Society}, timestamp = {2019-09-27T17:39:21.000+0200}, title = {On CMOS bridge fault modeling and test pattern evaluation.}, url = {http://dblp.uni-trier.de/db/conf/vts/vts1993.html#DiJ93}, year = 1993 }