%0 Conference Paper %1 conf/memsys/HameedMC17 %A Hameed, Fazal %A Menard, Christian %A Castrillón, Jerónimo %B MEMSYS %D 2017 %I ACM %K dblp %P 141-151 %T Efficient STT-RAM last-level-cache architecture to replace DRAM cache. %U http://dblp.uni-trier.de/db/conf/memsys/memsys2017.html#HameedMC17 %@ 978-1-4503-5335-9

@inproceedings{conf/memsys/HameedMC17, added-at = {2019-09-16T00:00:00.000+0200}, author = {Hameed, Fazal and Menard, Christian and Castrillón, Jerónimo}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/23e99173e512a1117392f94ba5788c82f/dblp}, booktitle = {MEMSYS}, crossref = {conf/memsys/2017}, ee = {https://doi.org/10.1145/3132402.3132414}, interhash = {9be80a4e9a08b06913930664bd2ccfdb}, intrahash = {3e99173e512a1117392f94ba5788c82f}, isbn = {978-1-4503-5335-9}, keywords = {dblp}, pages = {141-151}, publisher = {ACM}, timestamp = {2019-09-27T21:22:31.000+0200}, title = {Efficient STT-RAM last-level-cache architecture to replace DRAM cache.}, url = {http://dblp.uni-trier.de/db/conf/memsys/memsys2017.html#HameedMC17}, year = 2017 }