%0 Journal Article %1 journals/tvlsi/ChaturvediH05 %A Chaturvedi, Rishi %A Hu, Jiang %D 2005 %J IEEE Trans. VLSI Syst. %K dblp %N 6 %P 750-754 %T An efficient merging scheme for prescribed skew clock routing. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi13.html#ChaturvediH05 %V 13

@article{journals/tvlsi/ChaturvediH05, added-at = {2016-03-15T00:00:00.000+0100}, author = {Chaturvedi, Rishi and Hu, Jiang}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/248f5c395bcaf565250e3bf326f8ecfad/dblp}, ee = {http://dx.doi.org/10.1109/TVLSI.2005.848821}, interhash = {99f366e978f8257b4ff526c19371055e}, intrahash = {48f5c395bcaf565250e3bf326f8ecfad}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 6, pages = {750-754}, timestamp = {2016-03-16T10:32:01.000+0100}, title = {An efficient merging scheme for prescribed skew clock routing.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi13.html#ChaturvediH05}, volume = 13, year = 2005 }