%0 Journal Article %1 journals/tcad/LahiriRD04a %A Lahiri, Kanishka %A Raghunathan, Anand %A Dey, Sujit %D 2004 %J IEEE Trans. on CAD of Integrated Circuits and Systems %K dblp %N 6 %P 952-961 %T Design space exploration for optimizing on-chip communication architectures. %U http://dblp.uni-trier.de/db/journals/tcad/tcad23.html#LahiriRD04a %V 23

@article{journals/tcad/LahiriRD04a, added-at = {2016-03-18T00:00:00.000+0100}, author = {Lahiri, Kanishka and Raghunathan, Anand and Dey, Sujit}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/290c3ec07a7d17acdcbfce8cae87e2d0b/dblp}, ee = {http://dx.doi.org/10.1109/TCAD.2004.828127}, interhash = {7ea47e5e9f87f3bfb9c9f606a7e4b6c9}, intrahash = {90c3ec07a7d17acdcbfce8cae87e2d0b}, journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, keywords = {dblp}, number = 6, pages = {952-961}, timestamp = {2016-03-19T10:32:42.000+0100}, title = {Design space exploration for optimizing on-chip communication architectures.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad23.html#LahiriRD04a}, volume = 23, year = 2004 }