%0 Conference Paper %1 conf/fpl/JaniszewskiMH04 %A Janiszewski, Ireneusz %A Meuth, Hermann %A Hoppe, Bernhard %B FPL %D 2004 %E Becker, Jürgen %E Platzner, Marco %E Vernalde, Serge %I Springer %K dblp %P 933-937 %T FPGA-Efficient Hybrid LUT/CORDIC Architecture. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2004.html#JaniszewskiMH04 %V 3203 %@ 3-540-22989-2

@inproceedings{conf/fpl/JaniszewskiMH04, added-at = {2017-05-21T00:00:00.000+0200}, author = {Janiszewski, Ireneusz and Meuth, Hermann and Hoppe, Bernhard}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/251637e3f1127f6e77a483c0fa48aaeac/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2004}, editor = {Becker, Jürgen and Platzner, Marco and Vernalde, Serge}, ee = {https://doi.org/10.1007/978-3-540-30117-2_102}, interhash = {6aaac815f26c995bf350d88efb5d0c61}, intrahash = {51637e3f1127f6e77a483c0fa48aaeac}, isbn = {3-540-22989-2}, keywords = {dblp}, pages = {933-937}, publisher = {Springer}, series = {Lecture Notes in Computer Science}, timestamp = {2019-09-27T14:36:20.000+0200}, title = {FPGA-Efficient Hybrid LUT/CORDIC Architecture.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2004.html#JaniszewskiMH04}, volume = 3203, year = 2004 }