%0 Journal Article %1 journals/tvlsi/ZarandiMHSAS15 %A Zarandi, Azadeh Alsadat Emrani %A Molahosseini, Amir Sabbagh %A Hosseinzadeh, Mehdi %A Sorouri, Saeid %A Antão, Samuel %A Sousa, Leonel %D 2015 %J IEEE Trans. VLSI Syst. %K dblp %N 2 %P 374-378 %T Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi23.html#ZarandiMHSAS15 %V 23

@article{journals/tvlsi/ZarandiMHSAS15, added-at = {2015-02-24T00:00:00.000+0100}, author = {Zarandi, Azadeh Alsadat Emrani and Molahosseini, Amir Sabbagh and Hosseinzadeh, Mehdi and Sorouri, Saeid and Antão, Samuel and Sousa, Leonel}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/23c29dd37e986257379fd42b864cd6282/dblp}, ee = {http://dx.doi.org/10.1109/TVLSI.2014.2305392}, interhash = {5e47d7714172051f13761cdb4ee0e3e6}, intrahash = {3c29dd37e986257379fd42b864cd6282}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 2, pages = {374-378}, timestamp = {2016-02-02T02:13:23.000+0100}, title = {Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi23.html#ZarandiMHSAS15}, volume = 23, year = 2015 }