%0 Journal Article %1 journals/tcad/CabodiCPPV19 %A Cabodi, Gianpiero %A Camurati, Paolo %A Palena, Marco %A Pasini, Paolo %A Vendraminetto, Danilo %D 2019 %J IEEE Trans. on CAD of Integrated Circuits and Systems %K dblp %N 2 %P 380-384 %T Logic Synthesis for Interpolant Circuit Compaction. %U http://dblp.uni-trier.de/db/journals/tcad/tcad38.html#CabodiCPPV19 %V 38

@article{journals/tcad/CabodiCPPV19, added-at = {2019-02-13T00:00:00.000+0100}, author = {Cabodi, Gianpiero and Camurati, Paolo and Palena, Marco and Pasini, Paolo and Vendraminetto, Danilo}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2552ac6b101588cf9eb5f69d194be2d83/dblp}, ee = {https://doi.org/10.1109/TCAD.2018.2808229}, interhash = {5de65dddc5184ed4c7b15731ec6d7f83}, intrahash = {552ac6b101588cf9eb5f69d194be2d83}, journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, keywords = {dblp}, number = 2, pages = {380-384}, timestamp = {2019-09-27T08:26:54.000+0200}, title = {Logic Synthesis for Interpolant Circuit Compaction.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad38.html#CabodiCPPV19}, volume = 38, year = 2019 }