%0 Journal Article %1 journals/tcas/ShaoWCXQYS07 %A Shao, Zili %A Wang, Meng %A Chen, Ying %A Xue, Chun %A Qiu, Meikang %A Yang, Laurence T. %A Sha, Edwin Hsing-Mean %D 2007 %J IEEE Trans. on Circuits and Systems %K dblp %N 5 %P 445-449 %T Real-Time Dynamic Voltage Loop Scheduling for Multi-Core Embedded Systems. %U http://dblp.uni-trier.de/db/journals/tcas/tcasII54.html#ShaoWCXQYS07 %V 54-II

@article{journals/tcas/ShaoWCXQYS07, added-at = {2013-10-25T00:00:00.000+0200}, author = {Shao, Zili and Wang, Meng and Chen, Ying and Xue, Chun and Qiu, Meikang and Yang, Laurence T. and Sha, Edwin Hsing-Mean}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/29922d911a452bea08b427c0c8b844cea/dblp}, ee = {http://dx.doi.org/10.1109/TCSII.2007.892215}, interhash = {49498c87ffb1b6e078b4a6d0aa6b36e5}, intrahash = {9922d911a452bea08b427c0c8b844cea}, journal = {IEEE Trans. on Circuits and Systems}, keywords = {dblp}, number = 5, pages = {445-449}, timestamp = {2016-02-02T02:19:19.000+0100}, title = {Real-Time Dynamic Voltage Loop Scheduling for Multi-Core Embedded Systems.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasII54.html#ShaoWCXQYS07}, volume = {54-II}, year = 2007 }