%0 Journal Article %1 journals/mvl/WilleGMD12 %A Wille, Robert %A Große, Daniel %A Miller, D. Michael %A Drechsler, Rolf %D 2012 %J Multiple-Valued Logic and Soft Computing %K dblp %N 4 %P 361-378 %T Equivalence Checking of Reversible Circuits. %U http://dblp.uni-trier.de/db/journals/mvl/mvl19.html#WilleGMD12 %V 19

@article{journals/mvl/WilleGMD12, added-at = {2012-09-07T00:00:00.000+0200}, author = {Wille, Robert and Große, Daniel and Miller, D. Michael and Drechsler, Rolf}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2c4db34b531aafe510bd2b4f6da095ee7/dblp}, ee = {http://www.oldcitypublishing.com/MVLSC/MVLSCabstracts/MVLSC19.4abstracts/MVLSCv19n4p361-378Wille.html}, interhash = {471ceceac89e3d21bec2ad8c8267fd73}, intrahash = {c4db34b531aafe510bd2b4f6da095ee7}, journal = {Multiple-Valued Logic and Soft Computing}, keywords = {dblp}, number = 4, pages = {361-378}, timestamp = {2016-02-02T03:26:08.000+0100}, title = {Equivalence Checking of Reversible Circuits.}, url = {http://dblp.uni-trier.de/db/journals/mvl/mvl19.html#WilleGMD12}, volume = 19, year = 2012 }