%0 Journal Article %1 journals/tvlsi/MuraliAMCBMR07 %A Murali, Srinivasan %A Atienza, David %A Meloni, Paolo %A Carta, Salvatore %A Benini, Luca %A Micheli, Giovanni De %A Raffo, Luigi %D 2007 %J IEEE Trans. VLSI Syst. %K dblp %N 8 %P 869-880 %T Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi15.html#MuraliAMCBMR07 %V 15

@article{journals/tvlsi/MuraliAMCBMR07, added-at = {2007-11-04T00:00:00.000+0100}, author = {Murali, Srinivasan and Atienza, David and Meloni, Paolo and Carta, Salvatore and Benini, Luca and Micheli, Giovanni De and Raffo, Luigi}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2d11f0d08e9759ead486fc2a5f0e6332d/dblp}, ee = {http://dx.doi.org/10.1109/TVLSI.2007.900742}, interhash = {3736e70122231070533078dd7a8a7f2d}, intrahash = {d11f0d08e9759ead486fc2a5f0e6332d}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 8, pages = {869-880}, timestamp = {2016-02-02T02:13:15.000+0100}, title = {Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi15.html#MuraliAMCBMR07}, volume = 15, year = 2007 }