%0 Journal Article %1 journals/jrm/YoshizawaHWM05 %A Yoshizawa, Shingo %A Hayasaka, Noboru %A Wada, Naoya %A Miyanaga, Yoshikazu %D 2005 %J JRM %K dblp %N 4 %P 447-455 %T VLSI Architecture for Robust Speech Recognition Systems and its Implementation on a Verification Platform. %U http://dblp.uni-trier.de/db/journals/jrm/jrm17.html#YoshizawaHWM05 %V 17

@article{journals/jrm/YoshizawaHWM05, added-at = {2016-12-26T00:00:00.000+0100}, author = {Yoshizawa, Shingo and Hayasaka, Noboru and Wada, Naoya and Miyanaga, Yoshikazu}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/22099ca97702435dc0919c97d9a8ce55a/dblp}, ee = {http://dx.doi.org/10.20965/jrm.2005.p0447}, interhash = {1ed19ea15b9585762a220e9e5c300391}, intrahash = {2099ca97702435dc0919c97d9a8ce55a}, journal = {JRM}, keywords = {dblp}, number = 4, pages = {447-455}, timestamp = {2016-12-29T10:32:38.000+0100}, title = {VLSI Architecture for Robust Speech Recognition Systems and its Implementation on a Verification Platform.}, url = {http://dblp.uni-trier.de/db/journals/jrm/jrm17.html#YoshizawaHWM05}, volume = 17, year = 2005 }