%0 Journal Article %1 journals/vlsisp/Valero-GarciaNLVL92 %A Valero-García, Miguel %A Navarro, Juan J. %A Llabería, José María %A Valero, Mateo %A Lang, Tomás %D 1992 %J VLSI Signal Processing %K dblp %N 1 %P 7-25 %T A method for implementation of one-dimensional systolic algorithms with data contraflow using pipelined functional units. %U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp4.html#Valero-GarciaNLVL92 %V 4

@article{journals/vlsisp/Valero-GarciaNLVL92, added-at = {2019-06-02T00:00:00.000+0200}, author = {Valero-García, Miguel and Navarro, Juan J. and Llabería, José María and Valero, Mateo and Lang, Tomás}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/299d67e319ef8677866b377d16f18ca88/dblp}, ee = {https://www.wikidata.org/entity/Q61731068}, interhash = {11400e023634bb3215c216e8b9dfb0a4}, intrahash = {99d67e319ef8677866b377d16f18ca88}, journal = {VLSI Signal Processing}, keywords = {dblp}, number = 1, pages = {7-25}, timestamp = {2019-09-27T11:06:25.000+0200}, title = {A method for implementation of one-dimensional systolic algorithms with data contraflow using pipelined functional units.}, url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp4.html#Valero-GarciaNLVL92}, volume = 4, year = 1992 }