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Accurate simulations of the interplay between process and statistical variability for nanoscale FinFET-based SRAM cell stability.

, , , , and . ESSDERC, page 349-352. IEEE, (2014)

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SRAM device and cell co-design considerations in a 14nm SOI FinFET technology., , , , , , , and . ISCAS, page 2339-2342. IEEE, (2013)Accurate simulations of the interplay between process and statistical variability for nanoscale FinFET-based SRAM cell stability., , , , and . ESSDERC, page 349-352. IEEE, (2014)A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond., , , , , , , , , and . CoRR, (2019)Capturing intrinsic parameter fluctuations using the PSP compact model., , , , , , , and . DATE, page 650-653. IEEE, (2010)Impact of statistical variability and charge trapping on 14 nm SOI FinFET SRAM cell stability., , , , , , and . ESSDERC, page 234-237. IEEE, (2013)Statistical variability in 14-nm node SOI FinFETs and its impact on corresponding 6T-SRAM cell design., , , , and . ESSDERC, page 113-116. IEEE, (2012)Statistical-Variability Compact-Modeling Strategies for BSIM4 and PSP., , , , , , , and . IEEE Design & Test of Computers, 27 (2): 26-35 (2010)Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology., , , , , and . IEEE Design & Test, 30 (6): 18-28 (2013)Nanowire transistor solutions for 5nm and beyond., , , , , , and . ISQED, page 269-274. IEEE, (2016)