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%0 Journal Article
%1 journals/tvlsi/TakeuchiYKKMKYS08
%A Takeuchi, Kan
%A Yoshikawa, A.
%A Komoda, M.
%A Kotani, K.
%A Matsushita, Hiroaki
%A Katsuki, Yusaku
%A Yamamoto, Y.
%A Sato, Takao
%D 2008
%J IEEE Trans. VLSI Syst.
%K dblp
%N 11
%P 1559-1566
%T Clock-Skew Test Module for Exploring Reliable Clock-Distribution Under Process and Global Voltage-Temperature Variations.
%U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi16.html#TakeuchiYKKMKYS08
%V 16
@article{journals/tvlsi/TakeuchiYKKMKYS08,
added-at = {2012-02-06T00:00:00.000+0100},
author = {Takeuchi, Kan and Yoshikawa, A. and Komoda, M. and Kotani, K. and Matsushita, Hiroaki and Katsuki, Yusaku and Yamamoto, Y. and Sato, Takao},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2f6f942fa8bb4a147e2fe203991130072/dblp},
ee = {http://dx.doi.org/10.1109/TVLSI.2008.2000975},
interhash = {eaa9972b7252fb67bd4b1d483e261ad3},
intrahash = {f6f942fa8bb4a147e2fe203991130072},
journal = {IEEE Trans. VLSI Syst.},
keywords = {dblp},
number = 11,
pages = {1559-1566},
timestamp = {2016-02-02T02:13:34.000+0100},
title = {Clock-Skew Test Module for Exploring Reliable Clock-Distribution Under Process and Global Voltage-Temperature Variations.},
url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi16.html#TakeuchiYKKMKYS08},
volume = 16,
year = 2008
}
