A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network.
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%0 Journal Article
%1 journals/jssc/ShiYHCQLWW14
%A Shi, Cong
%A Yang, Jie
%A Han, Ye
%A Cao, Zhongxiang
%A Qin, Qi
%A Liu, Liyuan
%A Wu, Nanjian
%A Wang, Zhihua
%D 2014
%J J. Solid-State Circuits
%K dblp
%N 9
%P 2067-2082
%T A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network.
%U http://dblp.uni-trier.de/db/journals/jssc/jssc49.html#ShiYHCQLWW14
%V 49
@article{journals/jssc/ShiYHCQLWW14,
added-at = {2014-10-08T00:00:00.000+0200},
author = {Shi, Cong and Yang, Jie and Han, Ye and Cao, Zhongxiang and Qin, Qi and Liu, Liyuan and Wu, Nanjian and Wang, Zhihua},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/213d7efbc2ba0f75c456b6ca245486be9/dblp},
ee = {http://dx.doi.org/10.1109/JSSC.2014.2332134},
interhash = {99428b090c2b31aef86d1f1243cebc97},
intrahash = {13d7efbc2ba0f75c456b6ca245486be9},
journal = {J. Solid-State Circuits},
keywords = {dblp},
number = 9,
pages = {2067-2082},
timestamp = {2016-02-02T09:37:04.000+0100},
title = {A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc49.html#ShiYHCQLWW14},
volume = 49,
year = 2014
}
