%0 Journal Article %1 journals/tcad/Sapatnekar96 %A Sapatnekar, Sachin S. %D 1996 %J IEEE Trans. on CAD of Integrated Circuits and Systems %K dblp %N 8 %P 1001-1011 %T Wire sizing as a convex optimization problem: exploring the area-delay tradeoff. %U http://dblp.uni-trier.de/db/journals/tcad/tcad15.html#Sapatnekar96 %V 15

@article{journals/tcad/Sapatnekar96, added-at = {2018-11-02T00:00:00.000+0100}, author = {Sapatnekar, Sachin S.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2c52ac70dcb67888d177fcc67148148b4/dblp}, ee = {https://doi.org/10.1109/43.511579}, interhash = {69f0f8fe39d1e73c2c4b4e39bbd644e2}, intrahash = {c52ac70dcb67888d177fcc67148148b4}, journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, keywords = {dblp}, number = 8, pages = {1001-1011}, timestamp = {2019-09-27T08:26:50.000+0200}, title = {Wire sizing as a convex optimization problem: exploring the area-delay tradeoff.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad15.html#Sapatnekar96}, volume = 15, year = 1996 }