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%0 Journal Article
%1 journals/tvlsi/SheikhEES17
%A Sheikh, Ahmad T.
%A El-Maleh, Aiman H.
%A Elrabaa, Muhammad E. S.
%A Sait, Sadiq M.
%D 2017
%J IEEE Trans. VLSI Syst.
%K dblp
%N 1
%P 224-237
%T A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy.
%U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#SheikhEES17
%V 25
@article{journals/tvlsi/SheikhEES17,
added-at = {2017-01-04T00:00:00.000+0100},
author = {Sheikh, Ahmad T. and El-Maleh, Aiman H. and Elrabaa, Muhammad E. S. and Sait, Sadiq M.},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2cfc0f3f1cff444e4bfd44c4555baacae/dblp},
ee = {http://dx.doi.org/10.1109/TVLSI.2016.2569532},
interhash = {4fe56f2e1db05535880a78ff6a9c2f8a},
intrahash = {cfc0f3f1cff444e4bfd44c4555baacae},
journal = {IEEE Trans. VLSI Syst.},
keywords = {dblp},
number = 1,
pages = {224-237},
timestamp = {2017-01-05T10:32:32.000+0100},
title = {A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy.},
url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#SheikhEES17},
volume = 25,
year = 2017
}
