%0 Journal Article %1 journals/tvlsi/WuGKSLZS16 %A Wu, Chundong %A Goh, Wang Ling %A Kok, Chiang Liang %A Siek, Liter %A Lam, Yat-Hei %A Zhu, Xi %A Singh, Ravinder Pal %D 2016 %J IEEE Trans. VLSI Syst. %K dblp %N 12 %P 3543-3547 %T Asymmetrical Dead-Time Control Driver for Buck Regulator. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi24.html#WuGKSLZS16 %V 24

@article{journals/tvlsi/WuGKSLZS16, added-at = {2018-11-02T00:00:00.000+0100}, author = {Wu, Chundong and Goh, Wang Ling and Kok, Chiang Liang and Siek, Liter and Lam, Yat-Hei and Zhu, Xi and Singh, Ravinder Pal}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/27b0a9145fae79f61610d4ff79c115e26/dblp}, ee = {https://doi.org/10.1109/TVLSI.2016.2551321}, interhash = {3a7c17849987b940dd6f087866fb9162}, intrahash = {7b0a9145fae79f61610d4ff79c115e26}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 12, pages = {3543-3547}, timestamp = {2019-09-27T06:53:33.000+0200}, title = {Asymmetrical Dead-Time Control Driver for Buck Regulator.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi24.html#WuGKSLZS16}, volume = 24, year = 2016 }