This paper considers the implementation of a continuous-time low-pass single-bit ΔΣ analog-digital converter (ADC) for radar applications. By taking advantage of the high transit frequency of a 0.25μm SiGe BiCMOS technology, the 3rd-order modulator operates at 1.92GHz and achieves 77.8dB SNDR within a bandwidth of 15MHz, when simulating the sensitive circuit parts on transistor level. Thanks to the inherent linearity of single-bit digital-analog converter (DAC), high linearity of 90dB spurious-free dynamic range (SFDR) can be achieved.
%0 Conference Paper
%1 6572084
%A Chu, C.
%A Brückner, T.
%A Kauffman, J. G.
%A Anders, J.
%A Becker, J.
%A Ortmanns, M.
%B 2013 IEEE International Symposium on Circuits and Systems (ISCAS)
%D 2013
%K delta modulators sigma
%P 1268-1271
%R 10.1109/ISCAS.2013.6572084
%T Analysis and design of high speed/high linearity continuous time delta-sigma modulator
%U https://ieeexplore.ieee.org/document/6572084/
%X This paper considers the implementation of a continuous-time low-pass single-bit ΔΣ analog-digital converter (ADC) for radar applications. By taking advantage of the high transit frequency of a 0.25μm SiGe BiCMOS technology, the 3rd-order modulator operates at 1.92GHz and achieves 77.8dB SNDR within a bandwidth of 15MHz, when simulating the sensitive circuit parts on transistor level. Thanks to the inherent linearity of single-bit digital-analog converter (DAC), high linearity of 90dB spurious-free dynamic range (SFDR) can be achieved.
@inproceedings{6572084,
abstract = {This paper considers the implementation of a continuous-time low-pass single-bit ΔΣ analog-digital converter (ADC) for radar applications. By taking advantage of the high transit frequency of a 0.25μm SiGe BiCMOS technology, the 3rd-order modulator operates at 1.92GHz and achieves 77.8dB SNDR within a bandwidth of 15MHz, when simulating the sensitive circuit parts on transistor level. Thanks to the inherent linearity of single-bit digital-analog converter (DAC), high linearity of 90dB spurious-free dynamic range (SFDR) can be achieved.},
added-at = {2020-10-11T10:16:15.000+0200},
author = {{Chu}, C. and {Brückner}, T. and {Kauffman}, J. G. and {Anders}, J. and {Becker}, J. and {Ortmanns}, M.},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2f3538fc5c9529c65cd0c2aff2fb265ed/jens.anders},
booktitle = {2013 IEEE International Symposium on Circuits and Systems (ISCAS)},
doi = {10.1109/ISCAS.2013.6572084},
interhash = {4e0a77bf784bc646b66850924289e82c},
intrahash = {f3538fc5c9529c65cd0c2aff2fb265ed},
issn = {2158-1525},
keywords = {delta modulators sigma},
month = may,
pages = {1268-1271},
timestamp = {2020-10-12T13:45:14.000+0200},
title = {Analysis and design of high speed/high linearity continuous time delta-sigma modulator},
url = {https://ieeexplore.ieee.org/document/6572084/},
year = 2013
}
