Clock jitter sensitivity is a well-known drawback of continuous-time ΣΔ modulators. Although there exist various methods to alleviate the jitter influence, most are only effective in reducing noise incurred by out-of-band quantization noise. However, due to the steadily increasing signal frequency in receiver applications, the dominant jitter influence rather originates from the mixing between the close to in-band interferers and the close-in clock phase noise, either in a mixer or in the DAC of a bandpass ΣΔ modulator. This mixing results in additional in-band noise which cannot be reduced by existing solutions. In this paper, we use a reconfigurable digital filtering method for close to in-band interferer suppression in bandpass ΣΔ modulators, and demonstrate its effectiveness in improving phase noise tolerance through simulation. Additionally, a technique to simplify the implementation of the digital filters is proposed.
%0 Conference Paper
%1 8050482
%A Chi, J.
%A Wagner, J.
%A Anders, J.
%A Ortmanns, M.
%B 2017 IEEE International Symposium on Circuits and Systems (ISCAS)
%D 2017
%K Delta Sigma interference modulators suppressions
%P 1-4
%R 10.1109/ISCAS.2017.8050482
%T Digital interferer suppression and jitter reduction in continuous-time bandpass ΣΔ modulators
%U https://ieeexplore.ieee.org/document/8050482/
%X Clock jitter sensitivity is a well-known drawback of continuous-time ΣΔ modulators. Although there exist various methods to alleviate the jitter influence, most are only effective in reducing noise incurred by out-of-band quantization noise. However, due to the steadily increasing signal frequency in receiver applications, the dominant jitter influence rather originates from the mixing between the close to in-band interferers and the close-in clock phase noise, either in a mixer or in the DAC of a bandpass ΣΔ modulator. This mixing results in additional in-band noise which cannot be reduced by existing solutions. In this paper, we use a reconfigurable digital filtering method for close to in-band interferer suppression in bandpass ΣΔ modulators, and demonstrate its effectiveness in improving phase noise tolerance through simulation. Additionally, a technique to simplify the implementation of the digital filters is proposed.
@inproceedings{8050482,
abstract = {Clock jitter sensitivity is a well-known drawback of continuous-time ΣΔ modulators. Although there exist various methods to alleviate the jitter influence, most are only effective in reducing noise incurred by out-of-band quantization noise. However, due to the steadily increasing signal frequency in receiver applications, the dominant jitter influence rather originates from the mixing between the close to in-band interferers and the close-in clock phase noise, either in a mixer or in the DAC of a bandpass ΣΔ modulator. This mixing results in additional in-band noise which cannot be reduced by existing solutions. In this paper, we use a reconfigurable digital filtering method for close to in-band interferer suppression in bandpass ΣΔ modulators, and demonstrate its effectiveness in improving phase noise tolerance through simulation. Additionally, a technique to simplify the implementation of the digital filters is proposed.},
added-at = {2020-10-11T09:45:32.000+0200},
author = {{Chi}, J. and {Wagner}, J. and {Anders}, J. and {Ortmanns}, M.},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2ee04853ef602f9e6498e619a0a82695f/jens.anders},
booktitle = {2017 IEEE International Symposium on Circuits and Systems (ISCAS)},
doi = {10.1109/ISCAS.2017.8050482},
interhash = {1d71069e6d784d4b42e66ddad70b248a},
intrahash = {ee04853ef602f9e6498e619a0a82695f},
issn = {2379-447X},
keywords = {Delta Sigma interference modulators suppressions},
month = may,
pages = {1-4},
timestamp = {2020-10-12T13:58:37.000+0200},
title = {Digital interferer suppression and jitter reduction in continuous-time bandpass ΣΔ modulators},
url = {https://ieeexplore.ieee.org/document/8050482/},
year = 2017
}
