This paper introduces an architecture and design for high resolution, high linearity Nyquist rate SAR ADCs requiring only a single simple calibration at startup. The proposed architecture benefits from an intrinsically linear 1.5 bit ΣΔ DAC to resolve the fine bits of the SAR ADC after a coarse conversion phase with a monotonically switched capacitive DAC. The ΣΔ DAC is also used for a single shot calibration of the coarse CDAC which therefore does not require good matching and can be sized solely upon noise requirements. A prototype was fabricated in 40 nm CMOS, with power supplies of 1.1 V and 2.5 V. It occupies an active area of only 0.074mm2. The prototype achieves a measured peak SFDR of 107 dB and a noise limited SNDR of 84.8 dB at 80 kS/s Nyquist rate operation. The core power consumption is 101 μW at 80 kS/s. In oversampling mode, the ADC achieves an SNDR above 90 dB over a 5 kHz bandwidth.
%0 Conference Paper
%1 8008494
%A AlMarashli, A.
%A Anders, J.
%A Becker, J.
%A Ortmanns, M.
%B 2017 Symposium on VLSI Circuits
%D 2017
%K SAR ADC from:jens.anders
%P C240-C241
%R 10.23919/VLSIC.2017.8008494
%T A 107 dB SFDR, 80 kS/s Nyquist-rate SAR ADC using a hybrid capacitive and incremental ΣΔ DAC
%U https://ieeexplore.ieee.org/document/8008494/
%X This paper introduces an architecture and design for high resolution, high linearity Nyquist rate SAR ADCs requiring only a single simple calibration at startup. The proposed architecture benefits from an intrinsically linear 1.5 bit ΣΔ DAC to resolve the fine bits of the SAR ADC after a coarse conversion phase with a monotonically switched capacitive DAC. The ΣΔ DAC is also used for a single shot calibration of the coarse CDAC which therefore does not require good matching and can be sized solely upon noise requirements. A prototype was fabricated in 40 nm CMOS, with power supplies of 1.1 V and 2.5 V. It occupies an active area of only 0.074mm2. The prototype achieves a measured peak SFDR of 107 dB and a noise limited SNDR of 84.8 dB at 80 kS/s Nyquist rate operation. The core power consumption is 101 μW at 80 kS/s. In oversampling mode, the ADC achieves an SNDR above 90 dB over a 5 kHz bandwidth.
@inproceedings{8008494,
abstract = {This paper introduces an architecture and design for high resolution, high linearity Nyquist rate SAR ADCs requiring only a single simple calibration at startup. The proposed architecture benefits from an intrinsically linear 1.5 bit ΣΔ DAC to resolve the fine bits of the SAR ADC after a coarse conversion phase with a monotonically switched capacitive DAC. The ΣΔ DAC is also used for a single shot calibration of the coarse CDAC which therefore does not require good matching and can be sized solely upon noise requirements. A prototype was fabricated in 40 nm CMOS, with power supplies of 1.1 V and 2.5 V. It occupies an active area of only 0.074mm2. The prototype achieves a measured peak SFDR of 107 dB and a noise limited SNDR of 84.8 dB at 80 kS/s Nyquist rate operation. The core power consumption is 101 μW at 80 kS/s. In oversampling mode, the ADC achieves an SNDR above 90 dB over a 5 kHz bandwidth.},
added-at = {2020-10-12T15:54:10.000+0200},
author = {{AlMarashli}, A. and {Anders}, J. and {Becker}, J. and {Ortmanns}, M.},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2d6e0ff0369ac95f40813fa32531d8d72/iis},
booktitle = {2017 Symposium on VLSI Circuits},
doi = {10.23919/VLSIC.2017.8008494},
interhash = {67f4f0ebde1e46b0f3a1e2a4614c03c7},
intrahash = {d6e0ff0369ac95f40813fa32531d8d72},
keywords = {SAR ADC from:jens.anders},
month = {June},
pages = {C240-C241},
timestamp = {2020-10-12T13:54:10.000+0200},
title = {A 107 dB SFDR, 80 kS/s Nyquist-rate SAR ADC using a hybrid capacitive and incremental ΣΔ DAC},
url = {https://ieeexplore.ieee.org/document/8008494/},
year = 2017
}
