A 10-bit 50 MS/s current mode based SAR ADC is presented in this paper. The SAR ADC uses a Gm stage which converts the input voltage to a current which is then processed in a current based binary search algorithm SAR loop. In comparison to the conventional switched capacitor SAR ADC structures, the sampling capacitor size is smaller than the total capacitance of the comparable SC-SAR ADCs. Moreover, this design does not require an external reference voltage to bias the Gm stage output. The presented current mode ADC is designed for an overall resolution of 10 bit over a Nyquist band from DC to 25 MHz. Measured results of the ADC fabricated in a 90 nm CMOS technology show an SNDR of 45 dB and SFDR of 58.4 dB, while consuming 6mW from a 1.2 /1.8V supply.
%0 Conference Paper
%1 7364355
%A Elkafrawy, A.
%A Anders, J.
%A Ortmanns, M.
%B 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC)
%D 2015
%K SAR ADC from:jens.anders
%P 1-4
%R 10.1109/NORCHIP.2015.7364355
%T A 10-bit reference free current mode SAR ADC with 58.4 dB SFDR at 50 MS/s in 90 nm CMOS
%U https://ieeexplore.ieee.org/document/7364355/
%X A 10-bit 50 MS/s current mode based SAR ADC is presented in this paper. The SAR ADC uses a Gm stage which converts the input voltage to a current which is then processed in a current based binary search algorithm SAR loop. In comparison to the conventional switched capacitor SAR ADC structures, the sampling capacitor size is smaller than the total capacitance of the comparable SC-SAR ADCs. Moreover, this design does not require an external reference voltage to bias the Gm stage output. The presented current mode ADC is designed for an overall resolution of 10 bit over a Nyquist band from DC to 25 MHz. Measured results of the ADC fabricated in a 90 nm CMOS technology show an SNDR of 45 dB and SFDR of 58.4 dB, while consuming 6mW from a 1.2 /1.8V supply.
@inproceedings{7364355,
abstract = {A 10-bit 50 MS/s current mode based SAR ADC is presented in this paper. The SAR ADC uses a Gm stage which converts the input voltage to a current which is then processed in a current based binary search algorithm SAR loop. In comparison to the conventional switched capacitor SAR ADC structures, the sampling capacitor size is smaller than the total capacitance of the comparable SC-SAR ADCs. Moreover, this design does not require an external reference voltage to bias the Gm stage output. The presented current mode ADC is designed for an overall resolution of 10 bit over a Nyquist band from DC to 25 MHz. Measured results of the ADC fabricated in a 90 nm CMOS technology show an SNDR of 45 dB and SFDR of 58.4 dB, while consuming 6mW from a 1.2 /1.8V supply.},
added-at = {2020-10-12T15:51:10.000+0200},
author = {{Elkafrawy}, A. and {Anders}, J. and {Ortmanns}, M.},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2d594a0b21e5fb1734d2b9f260c6cd214/iis},
booktitle = {2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC)},
doi = {10.1109/NORCHIP.2015.7364355},
interhash = {1344e6e83a5a20a40198ea1e5fd74856},
intrahash = {d594a0b21e5fb1734d2b9f260c6cd214},
keywords = {SAR ADC from:jens.anders},
month = oct,
pages = {1-4},
timestamp = {2020-10-12T13:51:10.000+0200},
title = {A 10-bit reference free current mode SAR ADC with 58.4 dB SFDR at 50 MS/s in 90 nm CMOS},
url = {https://ieeexplore.ieee.org/document/7364355/},
year = 2015
}
