%0 Conference Paper %1 mohamed2021noiseaware %A Mohamed, A. %A Djekic, D. %A Baumgärtner, L. %A Anders, J. %B ICECS 2021 - 28th IEEE International Conference on Electronics Circuits and Systems (ICECS) %D 2021 %K myown iis from:aymanmohamed %P 1-4 %T Noise-aware design methodology of ultra-low-noise transimpedance amplifiers %X In this paper, we present a detailed analysis of the noise performance of transimpedance amplifiers (TIAs) to enable the design of ultra-low-noise current sensing frontends. While prior research on TIA noise focused on the thermal noise of the differential pair, here, we explicitly include the flicker noise of all noise-critical transistors. Using our analysis, we show that flicker noise of the input differential pair can be a primary noise source under many practically relevant circumstances. Moreover, based on this extended analysis, we propose a complete design methodology for ultra-low-noise TIAs. To this end, we derive analytical noise equations that help to interpret and optimize the noise behavior of a TIA before performing detailed transistor-level simulations. The presented analytical model achieves high accuracy by including BSIM4 parameters of the target technology. The proposed model and design approach are verified by an example design of an ultra-low-noise TIA in a 180nm CMOS SOI technology.

@inproceedings{mohamed2021noiseaware, abstract = {In this paper, we present a detailed analysis of the noise performance of transimpedance amplifiers (TIAs) to enable the design of ultra-low-noise current sensing frontends. While prior research on TIA noise focused on the thermal noise of the differential pair, here, we explicitly include the flicker noise of all noise-critical transistors. Using our analysis, we show that flicker noise of the input differential pair can be a primary noise source under many practically relevant circumstances. Moreover, based on this extended analysis, we propose a complete design methodology for ultra-low-noise TIAs. To this end, we derive analytical noise equations that help to interpret and optimize the noise behavior of a TIA before performing detailed transistor-level simulations. The presented analytical model achieves high accuracy by including BSIM4 parameters of the target technology. The proposed model and design approach are verified by an example design of an ultra-low-noise TIA in a 180nm CMOS SOI technology.}, added-at = {2021-09-26T18:08:04.000+0200}, author = {{Mohamed}, A. and {Djekic}, D. and {Baumgärtner}, L. and {Anders}, J.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2b1516895d66615e2f40f37bd819b56e9/iis}, booktitle = {ICECS 2021 - 28th IEEE International Conference on Electronics Circuits and Systems (ICECS)}, interhash = {5aa42c816b49f65b1af88f82c00982bd}, intrahash = {b1516895d66615e2f40f37bd819b56e9}, keywords = {myown iis from:aymanmohamed}, month = nov, pages = {1-4}, timestamp = {2021-09-26T16:08:04.000+0200}, title = {Noise-aware design methodology of ultra-low-noise transimpedance amplifiers}, year = 2021 }