We present a high linearity 2-bit digital-to-analog converter (DAC) implemented in an InP/GaInAs DHBT technology. The DAC is based upon the current steering architecture. Cascode structure and layout techniques, i.e. static shuffling and dummy devices, have been used to enhance the linearity. The DAC exhibits static integral/differential nonlinearities of 5.5 × 10-3 LSB, equivalent to a resolution of 9.2 bits. Dynamic measurements qualitatively show proper behavior at 6 GS/s, while simulations with typical on-chip load exhibit sufficiently fast settling at 20 GS/s.
%0 Conference Paper
%1 Kraus_IPRM2010
%A Kraus, S.
%A Kallfass, I.
%A Makon, R. E.
%A Rosenzweig, J.
%A Driad, R.
%A Moyal, M.
%A Ritter, D.
%B 2010 22nd International Conference on Indium Phosphide and Related Materials (IPRM)
%D 2010
%K 2-bit bipolar circuit circuits;Physics;Sampling compounds;heterojunction compounds;high conversion;Resistors;DH-HEMTs;Heterojunction conversion;gallium converter;cascode current devices;static digital-to-analog integral-differential layout;digital-analogue linearity methods;Switches nonlinearities;InP-GaInAs;Linearity;Indium phosphide;Digital-analog shuffling;dummy state steering;DHBT structure;layout techniques;static transistors;Solid transistors;indium
%P 1-4
%R 10.1109/ICIPRM.2010.5516140
%T High linearity 2-bit current steering InP/GaInAs DHBT digital-to-analog converter
%X We present a high linearity 2-bit digital-to-analog converter (DAC) implemented in an InP/GaInAs DHBT technology. The DAC is based upon the current steering architecture. Cascode structure and layout techniques, i.e. static shuffling and dummy devices, have been used to enhance the linearity. The DAC exhibits static integral/differential nonlinearities of 5.5 × 10-3 LSB, equivalent to a resolution of 9.2 bits. Dynamic measurements qualitatively show proper behavior at 6 GS/s, while simulations with typical on-chip load exhibit sufficiently fast settling at 20 GS/s.
@inproceedings{Kraus_IPRM2010,
abstract = {We present a high linearity 2-bit digital-to-analog converter (DAC) implemented in an InP/GaInAs DHBT technology. The DAC is based upon the current steering architecture. Cascode structure and layout techniques, i.e. static shuffling and dummy devices, have been used to enhance the linearity. The DAC exhibits static integral/differential nonlinearities of 5.5 × 10-3 LSB, equivalent to a resolution of 9.2 bits. Dynamic measurements qualitatively show proper behavior at 6 GS/s, while simulations with typical on-chip load exhibit sufficiently fast settling at 20 GS/s.},
added-at = {2022-11-04T11:48:46.000+0100},
author = {{Kraus}, S. and {Kallfass}, I. and {Makon}, R. E. and {Rosenzweig}, J. and {Driad}, R. and {Moyal}, M. and {Ritter}, D.},
bdsk-url-1 = {https://doi.org/10.1109/ICIPRM.2010.5516140},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2adbb3abd4be8ef712efd36eba3a3a15d/ingmarkallfass},
booktitle = {2010 22nd International Conference on Indium Phosphide and Related Materials (IPRM)},
date-added = {2020-11-27 15:15:23 +0100},
date-modified = {2020-11-27 15:15:32 +0100},
doi = {10.1109/ICIPRM.2010.5516140},
interhash = {ea8fbe2b5e29e2cf21c457a14cb766c5},
intrahash = {adbb3abd4be8ef712efd36eba3a3a15d},
issn = {1092-8669},
keywords = {2-bit bipolar circuit circuits;Physics;Sampling compounds;heterojunction compounds;high conversion;Resistors;DH-HEMTs;Heterojunction conversion;gallium converter;cascode current devices;static digital-to-analog integral-differential layout;digital-analogue linearity methods;Switches nonlinearities;InP-GaInAs;Linearity;Indium phosphide;Digital-analog shuffling;dummy state steering;DHBT structure;layout techniques;static transistors;Solid transistors;indium},
month = May,
pages = {1-4},
timestamp = {2025-05-26T10:46:15.000+0200},
title = {High linearity 2-bit current steering InP/GaInAs DHBT digital-to-analog converter},
year = 2010
}
