The objective of this work is to generate higher bandwidth signals (around 80 GHz for 160 GS/s multi-level signals) by time interleaving of several Digital-to-Analog Converter (DAC) with analog multiplexer AMUX.
A circuit design of a 4-to-1 AMUX already exists on schematic level, this work deals with the layout design of the analog 'four-to-one'-multiplexer in a leading 130 nanometres BiCMOS technology. Appropriate placement of the single layout elements and development of a meaningful floorplan regarding symmetry and signal path with little parasitics are considered. And finally, the extracted layout is characterised and compared to the performance of the schematic to find the optimization potential.
%0 Generic
%1 Veeramalai.2019
%A Veeramalai, Vijayashankar
%B Studienarbeit
%D 2019
%K SA int
%N 1062
%T Layout and Analysis of a 4-to-1 Analog Multiplexer in a 130nm SiGe BiCMOS Technology
%X The objective of this work is to generate higher bandwidth signals (around 80 GHz for 160 GS/s multi-level signals) by time interleaving of several Digital-to-Analog Converter (DAC) with analog multiplexer AMUX.
A circuit design of a 4-to-1 AMUX already exists on schematic level, this work deals with the layout design of the analog 'four-to-one'-multiplexer in a leading 130 nanometres BiCMOS technology. Appropriate placement of the single layout elements and development of a meaningful floorplan regarding symmetry and signal path with little parasitics are considered. And finally, the extracted layout is characterised and compared to the performance of the schematic to find the optimization potential.
@misc{Veeramalai.2019,
abstract = {The objective of this work is to generate higher bandwidth signals (around 80 GHz for 160 GS/s multi-level signals) by time interleaving of several Digital-to-Analog Converter (DAC) with analog multiplexer AMUX.
A circuit design of a 4-to-1 AMUX already exists on schematic level, this work deals with the layout design of the analog 'four-to-one'-multiplexer in a leading 130 nanometres BiCMOS technology. Appropriate placement of the single layout elements and development of a meaningful floorplan regarding symmetry and signal path with little parasitics are considered. And finally, the extracted layout is characterised and compared to the performance of the schematic to find the optimization potential.},
added-at = {2020-06-19T15:00:47.000+0200},
author = {Veeramalai, Vijayashankar},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/29768733b9497a159636559bf77562141/wolfgangvogel},
interhash = {9c40f2d5b1c526f58ac77f92ae6db8c2},
intrahash = {9768733b9497a159636559bf77562141},
keywords = {SA int},
number = 1062,
series = {Studienarbeit},
timestamp = {2020-06-19T13:00:47.000+0200},
title = {Layout and Analysis of a 4-to-1 Analog Multiplexer in a 130nm SiGe BiCMOS Technology},
year = 2019
}
