A 10-bit 150 MS/s current mode based SAR ADC is presented in this paper. The SAR ADC uses a Gm stage which converts the input voltage to a current which is then processed in a current based binary search algorithm SAR loop. Compared to the conventional switched capacitor SAR ADC structures, the settling speed of the current mode DAC is faster than the switched capacitor counterpart. As a proof of concept, this current mode ADC is designed for an overall resolution of 10bit over a Nyquist band from DC to 75MHz. The simulation results of the schematic level implementation in 90nm CMOS technology show an SNDR of 53dB and ENOB of 8.5 bit, while consuming 15mW from a 1.2 /1.8 V supply.
%0 Conference Paper
%1 7251388
%A Elkafrawy, A.
%A Anders, J.
%A Ortmanns, M.
%B 2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
%D 2015
%K SAR ADC from:jens.anders
%P 274-277
%R 10.1109/PRIME.2015.7251388
%T A 10-bit 150MS/s current mode SAR ADC in 90nm CMOS
%U https://ieeexplore.ieee.org/document/7251388/
%X A 10-bit 150 MS/s current mode based SAR ADC is presented in this paper. The SAR ADC uses a Gm stage which converts the input voltage to a current which is then processed in a current based binary search algorithm SAR loop. Compared to the conventional switched capacitor SAR ADC structures, the settling speed of the current mode DAC is faster than the switched capacitor counterpart. As a proof of concept, this current mode ADC is designed for an overall resolution of 10bit over a Nyquist band from DC to 75MHz. The simulation results of the schematic level implementation in 90nm CMOS technology show an SNDR of 53dB and ENOB of 8.5 bit, while consuming 15mW from a 1.2 /1.8 V supply.
@inproceedings{7251388,
abstract = {A 10-bit 150 MS/s current mode based SAR ADC is presented in this paper. The SAR ADC uses a Gm stage which converts the input voltage to a current which is then processed in a current based binary search algorithm SAR loop. Compared to the conventional switched capacitor SAR ADC structures, the settling speed of the current mode DAC is faster than the switched capacitor counterpart. As a proof of concept, this current mode ADC is designed for an overall resolution of 10bit over a Nyquist band from DC to 75MHz. The simulation results of the schematic level implementation in 90nm CMOS technology show an SNDR of 53dB and ENOB of 8.5 bit, while consuming 15mW from a 1.2 /1.8 V supply.},
added-at = {2020-10-12T15:50:13.000+0200},
author = {{Elkafrawy}, A. and {Anders}, J. and {Ortmanns}, M.},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/27f230879ce59ac3fd371e45132fef99c/iis},
booktitle = {2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)},
doi = {10.1109/PRIME.2015.7251388},
interhash = {c6516bfa3e413717c7802720b031cad3},
intrahash = {7f230879ce59ac3fd371e45132fef99c},
keywords = {SAR ADC from:jens.anders},
month = {June},
pages = {274-277},
timestamp = {2020-10-12T13:50:13.000+0200},
title = {A 10-bit 150MS/s current mode SAR ADC in 90nm CMOS},
url = {https://ieeexplore.ieee.org/document/7251388/},
year = 2015
}
